A Chip Architecture for Compressive Sensing Based Detection of IC Trojans

DSpace/Manakin Repository

A Chip Architecture for Compressive Sensing Based Detection of IC Trojans

Citable link to this page

. . . . . .

Title: A Chip Architecture for Compressive Sensing Based Detection of IC Trojans
Author: Tsai, Yi-Min; Vlah, Dario; Chen, Liang-Gee; Huang, Kang-Yen; Gwon, Youngjune Lee; Kung, H.T. T.

Note: Order does not necessarily reflect citation order of authors.

Citation: Tsai, Yi-Min, Keng-Yen Huang, H. T. Kung, Dario Vlah, Youngjune Gwon, and Liang-Gee Chen. 2012. A chip architecture for compressive sensing based detection of IC trojans. 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, South Korea, May 20-23, 2012.
Full Text & Related Files:
Abstract: We present a chip architecture for a compressive sensing based method that can be used in conjunction with the JTAG standard to detect IC Trojans. The proposed architecture compresses chip output resulting from a large number of test vectors applied to a circuit under test (CUT). We describe our designs in sensing leakage power, computing random linear combinations under compressive sensing, and piggybacking these new functionalities on JTAG. Our architecture achieves approximately a 10× speedup and 1000× reduction in output bandwidth while incurring a small area overhead.
Other Sources: http://www.eecs.harvard.edu/~htk/publication/2012-sips-tsai-huang-kung-vlah-gwon-chen.pdf
Terms of Use: This article is made available under the terms and conditions applicable to Open Access Policy Articles, as set forth at http://nrs.harvard.edu/urn-3:HUL.InstRepos:dash.current.terms-of-use#OAP
Citable link to this page: http://nrs.harvard.edu/urn-3:HUL.InstRepos:10000895

Show full Dublin Core record

This item appears in the following Collection(s)

  • FAS Scholarly Articles [7103]
    Peer reviewed scholarly articles from the Faculty of Arts and Sciences of Harvard University
 
 

Search DASH


Advanced Search
 
 

Submitters