III-V 4D Transistors
| Title: | III-V 4D Transistors |
| Author: |
Gu, J.J.; Wang, Xinwei; Shao, J.; Neal, A.T.; Gordon, Roy Gerald; Manfra, M.J.; Ye, P.D.
Note: Order does not necessarily reflect citation order of authors. |
| Citation: | Gu, J. J., X. W. Wang, J. Shao, A.T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye. 2012. III-V 4D Transistors. In Proceedings of the 70th Annual Device Research Conference (DRC 2012), June 18-20, 2012, University Park, Pennsylvania. Piscataway: Ieee Press Books. |
| Full Text & Related Files: |
III-V 4D Transistors.ieeeDRC2012p1-2.pdf (545.6Kb; PDF) 
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| Abstract: | We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with \(3×4\) arrays show high drive current of \(1.35mA/ \mu m\) and high transconductance of \(0.85mS/ \mu m\). The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application. |
| Published Version: | doi:10.1109/DRC.2012.6256964 |
| Terms of Use: | This article is made available under the terms and conditions applicable to Open Access Policy Articles, as set forth at http://nrs.harvard.edu/urn-3:HUL.InstRepos:dash.current.terms-of-use#OAP |
| Citable link to this page: | http://nrs.harvard.edu/urn-3:HUL.InstRepos:10021409 |
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