III-V 4D Transistors

DSpace/Manakin Repository

III-V 4D Transistors

Show simple item record

dc.contributor.author Gu, J.J.
dc.contributor.author Wang, Xinwei
dc.contributor.author Shao, J.
dc.contributor.author Neal, A.T.
dc.contributor.author Gordon, Roy Gerald
dc.contributor.author Manfra, M.J.
dc.contributor.author Ye, P.D.
dc.date.accessioned 2012-12-07T21:42:50Z
dc.date.issued 2012
dc.identifier.citation Gu, J. J., X. W. Wang, J. Shao, A.T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye. 2012. III-V 4D Transistors. In Proceedings of the 70th Annual Device Research Conference (DRC 2012), June 18-20, 2012, University Park, Pennsylvania. Piscataway: Ieee Press Books. en_US
dc.identifier.isbn 9781467311632 en_US
dc.identifier.isbn 1467311634 en_US
dc.identifier.issn 1548-3770 en_US
dc.identifier.uri http://nrs.harvard.edu/urn-3:HUL.InstRepos:10021409
dc.description.abstract We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with \(3×4\) arrays show high drive current of \(1.35mA/ \mu m\) and high transconductance of \(0.85mS/ \mu m\). The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application. en_US
dc.description.sponsorship Chemistry and Chemical Biology en_US
dc.language.iso en_US en_US
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.relation.isversionof doi:10.1109/DRC.2012.6256964 en_US
dash.license OAP
dc.subject fabrication en_US
dc.subject indium gallium arsenide en_US
dc.subject indium phosphide en_US
dc.subject logic gates en_US
dc.subject MOSFETs en_US
dc.subject nanobioscience en_US
dc.subject nanoscale devices en_US
dc.subject III-V semiconductors en_US
dc.subject MOSFET en_US
dc.subject indium compounds en_US
dc.subject III-V 4D transistor en_US
dc.subject III-V gate-all-around nanowire MOSFET en_US
dc.subject InGaAs en_US
dc.subject RF application en_US
dc.subject drivability bottleneck en_US
dc.subject laterally integrated III-V 4D transistor en_US
dc.subject low-power logic application en_US
dc.subject nanowire device en_US
dc.subject transconductance en_US
dc.subject vertical stacking en_US
dc.subject vertically integrated III-V 4D transistor en_US
dc.title III-V 4D Transistors en_US
dc.type Monograph or Book en_US
dc.description.version Accepted Manuscript en_US
dc.relation.journal IEEE Device Research Conference, 2012 70th Annual en_US
dash.depositing.author Gordon, Roy Gerald
dc.date.available 2012-12-07T21:42:50Z

Files in this item

Files Size Format View
III-V 4D Transistors.ieeeDRC2012p1-2.pdf 532.8Kb PDF View/Open

This item appears in the following Collection(s)

  • FAS Scholarly Articles [6948]
    Peer reviewed scholarly articles from the Faculty of Arts and Sciences of Harvard University

Show simple item record

 
 

Search DASH


Advanced Search
 
 

Submitters