Low-Complexity Systolic V-BLAST Architecture

dc.contributor.author	Koike-Akino, Toshiaki
dc.date.accessioned	2009-03-27T12:59:44Z
dc.date.issued	2009
dc.identifier.citation	Toshiaki, Koike-Akino. Forthcoming. Low-Complexity systolic V-BLAST Architecture. IEEE Transactions on Wireless Communications.	en
dc.identifier.issn	1536-1276	en
dc.identifier.uri	http://nrs.harvard.edu/urn-3:HUL.InstRepos:2748552
dc.description.abstract	In multiple-input multiple-output systems, an ordered successive interference canceller, termed the vertical Bell laboratories space-time (V-BLAST) algorithm, offers good performance. This letter presents a low-complexity V-BLAST scheme suited for parallel implementation. The proposed scheme, using a greedy ordering, can achieve a performance comparable to that of V-BLAST with optimum ordering, while its computational complexity is lower than a linear detector.	en
dc.description.sponsorship	Engineering and Applied Sciences	en
dc.language.iso	en_US	en
dc.publisher	Institute of Electrical and Electronics Engineers	en
dc.relation.isversionof	http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7693	en
dash.license	OAP
dc.subject	MIMO	en
dc.subject	V-BLAST	en
dc.subject	greedy ordering	en
dc.title	Low-Complexity Systolic V-BLAST Architecture	en
dc.relation.journal	IEEE Transactions on Wireless Communications	en
dash.depositing.author	Koike-Akino, Toshiaki
dc.identifier.doi	10.1109/TWC.2009.070498
dash.contributor.affiliated	Koike-Akino, Toshiaki