III–V 4D transistors

We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/μm and high transconductance of 0.85mS/μm. The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.

Fabrication started with a 2 inch semi-insulating InP (100) substrate.As shown in Fig. 1(a), the following layers were grown sequentially on the InP substrate: a 100nm undoped InAlAs etch stop layer, an 80nm undoped InP sacrificial layer, and then three layers of 30nm In 0.53 Ga 0.47 As channel with a 40nm InP layer in between each channel layer.Source/drain implantation was carried out with two-step Si implantation at 20keV and 60keV with a dose of 1×10 14 cm -2 .Fin etching using a novel Cl 2 /O 2 chemistry was performed with pre-patterned ALD Al 2 O 3 as etch mask.The oxide mask offers much higher selectivity to InGaAs/InP and therefore allows the fabrication of taller fins with H fin =150nm.After fin etching, the sample was soaked in HCl:H 2 O (1:2) solution for nanowire release.The HCl based solution selectively removes the InP sacrificial layers underneath each of the InGaAs channel layers provided that the fins were patterned along (100) directions [1] .10nm Al 2 O 3 and 40nm WN was then grown by ALD after surface passivation.WN is a kind of conductive nitride with a high thermal stability and a high work function of ~4.6eV [4] .The ALD process offers smooth (rms roughness 0.2 ~ 0.3 nm), conformal (excellent conformality on a hole sample with 210:1 aspect ratio) and pure WN films with reasonably low conductivity (several mΩ• cm).Cr/Au gate was then defined through a liftoff process and used as the etch mask for the subsequent CF 4 /Ar based WN gate etch process.Finally, Au/Ge/Ni based ohmic contacts were formed by e-beam evaporation and liftoff process and the definition of testing pads concludes the fabrication process.All patterns were defined using a UHR Vistec VB6 e-beam lithography system.Fig. 1 shows the schematic diagram of the device structure as an orthographic projection and a cross-sectional view of the vertically stacked nanowires.Fig. 2 summarized key fabrication process steps.
Fig. 3 (a) shows the top view SEM image of a finished device, showing parallel integration of 4 nanowire stacks laterally on the wafer.Fig. 3 (b) shows the cross sectional TEM image of one of these stacks, showing the 3 vertical stacked nanowires.The Al 2 O 3 dielectric and WN gate metal was clearly observed around all the wires, confirming the conformality of the ALD process.Due to the non-vertical fin etching process, the W NW increases from ~20nm for layer 1, ~60nm for layer 2, to ~100nm for layer 3, with a fixed H NW of 30nm for all three layers defined by the MBE growth thickness.More vertical dry etching process is under development.However, the stacked nanowires with different size could also be beneficial for better linearity than the uniform wires for RF device applications [5] .Fig. 3(c) shows the vertical and lateral integration of a 3×4 InGaAs nanowire array.Fig. 4 shows the output characteristics of a typical device with 3×4 nanowire array with L ch =200nm.The maximum saturation current reaches ~3mA at V ds =1V and V gs =2V.Normalization by total perimeter of the 12 nanowires yields a high drive current of 1.35mA/µm.If normalized only by the average dimension (60nm), I ds ≈12mA/ µm.As shown in Fig. 5, peak transconductance of 0.6mS/µm and 0.85mS/µm (5.4mS/µm and 7.7mS/µm normalized by the average dimension) was obtained at V ds of 0.5V and 1V, respectively.
In conclusion, we fabricated for the first time vertically and laterally integrated III-V 4D transistors.III-V GAA nanowire MOSFETs with 3×4 arrays show high drive current of 1.35mA/µm and high transconductance of

Fig. 3
Fig. 3 (a) Top-view SEM image of a vertically stacked InGaAs GAA nanowire MOSFETs with 4 parallel nanowire stacks.AA' and BB' correspond to the direction in Fig. 1(a).(b) Cross sectional high resolution TEM image of a InGaAs nanowire stack.The nanowires are wrapped by 10nm ALD Al 2 O 3 gate dielectric and 40nm ALD WN metal gate.The W NW increase from layer 1 through layer 3 due to the non-vertical fin dry etching process.The W NW for layer 1, 2 and 3 are measured to be around 20, 60, and 100nm.The H NW for each layer is 30nm.Therefore the total perimeter of a 3×1array is ~540nm.(c) The cross sectional TEM image of the 3×4 nanowire array along A-A'.

Fig. 4
Fig. 4 Output characteristics of vertically stackedInGaAs GAA nanowire MOSFETs with 3×4 nanowire array.The maximum saturation current reaches 1.35mA/µm at V ds =1V and V gs =2V normalized by total perimeter of the nanowires.

Fig. 5
Fig.5g m -V gs of vertically stacked InGaAs GAA nanowire MOSFETs with 3×4 nanowire array.The maximum g m reaches 0.85mS/µm at V ds =1V and 0.6mS/µm at V ds =0.5V normalized by total perimeter of the nanowires.