Effects of Forming Gas Anneal on Ultrathin InGaAs Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors

metal-oxide-semiconductor field-effect transistors (MOSFETs) with 6nm nanowire thickness have been experimentally demonstrated at sub-80nm channel length. The effects of Forming Gas Anneal (FGA) on the performance of these devices have been systematically studied. The 30min 400 FGA (4% H 2 / 96% N 2 ) is found to improve the quality of the Al 2 O 3 /InGaAs interface, resulting in a subthreshold slope reduction over 20mV/dec (from 117mV/dec in average to 93mV/dec). Moreover, the improvement of interface quality also has positive impact on the on-state device performance. A scaling metrics study has been carried out for FGA treated devices with channel lengths down to 20 nm, indicating excellent gate


5) School of Materials Engineering, Purdue University, West Lafayette, IN 47907, U.S.A.
InGaAs gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) with 6nm nanowire thickness have been experimentally demonstrated at sub-80nm channel length. The effects of Forming Gas Anneal (FGA) on the performance of these devices have been systematically studied. The 30min 400 FGA (4% H 2 / 96% N 2 ) is found to improve the quality of the Al 2 O 3 /InGaAs interface, resulting in a subthreshold slope reduction over 20mV/dec (from 117mV/dec in average to 93mV/dec). Moreover, the improvement of interface quality also has positive impact on the on-state device performance. A scaling metrics study has been carried out for FGA treated devices with channel lengths down to 20 nm, indicating excellent gate electrostatic control. With the FGA passivation and the ultra-thin nanowire structure, InGaAs MOSFETs are promising for future logic applications. a) Author to whom correspondence should be addressed; electronic mail: yep@purdue.edu Recently, InGaAs has been considered as one of the promising channel materials for CMOS beyond the 10nm technology node because of its large electron mobility. 3D InGaAs devices such as fin field-effect transistors and the gate-all-around (GAA) metaloxide-semiconductor field effect transistors have been shown to offer large drive current and excellent immunity to short channel effects (SCE) [1][2][3][4][5][6]. In particular, the GAA MOSFETs provide the best gate electrostatic control and therefore the ultimate channel length (L ch ) scalability. It is known that better SCE control can be obtained by reducing the nanowire size, enabling further L ch scaling. InGaAs nanowires fabricated by top-down technology with sub-10nm wire dimension, either nanowire width (W NW ) or thickness (T NW ), have not been reported. On the other hand, the interface quality is one of the critical problems for III-V MOSFETs. Superior interface quality is required for optimizing both the on-state and off-state performance of MOSFETs. Al 2 O 3 is commonly used as the gate insulator for InGaAs MOSFETs for the relatively low interface trap density (D it ). Various passivation methods have been developed and optimized on the Al 2 O 3 /InGaAs interface such as (NH 4 ) 2 S passivation [7,8], surface nitridation [9, 10] and phosphor passivation [11]. Forming Gas Anneal is another common post metallization treatment used to improve the interface quality of Al 2 O 3 /InGaAs. Interface traps, oxide charges and border traps reduction after FGA have been reported by CV methods [12,13].
Recent study of effects of FGA on planar devices shows that on state performances such as drive current (I on ) and transconductance (g m ) are improved after FGA [14]. However, the impacts of FGA have not been studied in short channel devices with GAA structure.
The compatibility between FGA and other passivation methods have not been studied either.
In this letter, 20-80nm L ch short channel In 0.65 Ga 0.35 As GAA MOSFETs with 6nm T NW and 30nm W NW have been fabricated with or without FGA treatment. FGA offers improvement in the on-state and off-state performance of the devices. The reduction of subthreshold slope (SS) and the increase of g m and I on verify the improvement of the interface quality. The average interface trap density drops by 40% on average after FGA.
Moreover, SS and drain induced barrier lowering (DIBL) do not increase when L ch scales from 80nm down to 20nm, demonstrating the excellent scalability of InGaAs GAA MOSFET with sub-10nm nanowire dimension. It is also found that the 30min 400 FGA passivation is fully compatible with the (NH 4 ) 2 S passivation. The interface trap density is significantly improved in devices with (NH 4 ) 2 S passivation and FGA together than those with (NH 4 ) 2 S passivation only. image of an InGaAs nanowire with 6nm T NW . The fabrication process flow of the devices is shown in Figure 1 (b). The top-down fabrication process is similar to that demonstrated in [4]. The starting material is a 2 inch semi-insulating InP substrate. 100nm undoped In 0.52 Al 0.48 As etch stop layer, 80nm undoped InP layer, 10 nm undoped In 0.65 Ga 0.35 As channel layer and 2 nm undoped InP layer were sequentially grown by molecular beam epitaxy. Source/drain implantation was performed at an energy of 20keV and a dose of 10 14 cm -2 , followed by dopant activation at 600 for 15 seconds in nitrogen ambient.
After fabricating nanowire fins using BCl 3 /Ar reactive ion etching, HCl based release process was performed to create the free-standing InGaAs nanowires. Before the gate stack deposition, 10% (NH 4 ) 2 S passivation was performed. The gate dielectric is 5nm atomic layer deposited (ALD) Al 2 O 3 to study the effect of FGA on Al 2 O 3 /InGaAs interface while maintaining a low gate leakage current. Following ALD WN gate metallization process, the devices are divided into two groups. One is treated with 30min 400 FGA (4% H 2 / 96% N 2 ) and the other serves as the control group. After gate etch process, source/drain contacts were formed with Au/Ge/Ni alloy. Each device has four nanowires fabricated in parallel. All patterns were defined by a Vistec UHR electron beam lithography system. FGA shows an 89% increase in on-current (I on ) at V ds = V gs -V T = 0.8V and the SS of device with FGA is 93mV/dec, which is 23mV/dec smaller than that of device without FGA. Maximum g m of device with FGA is also found to be 59% larger than that of control device without FGA. After being normalized by the perimeter of the nanowire, the best I on and peak g m at V ds = V gs -V T = 1V is 505 A/ m and 665 S/um, respectively.
The saturation-currents of devices in this work are lower compared to InGaAs GAA MOSFETs with 30nm T NW and the same W NW and L ch [4]. The reduction in drive current is attributed to the larger impact of surface roughness which decreases the channel mobility. Details of the transport properties of the ultra-thin nanowires are under investigation.
To study the effects of FGA, the average SS, threshold voltage V T , and I on of InGaAs GAA MOSFETs with L ch between 20nm and 80nm have been extracted. The threshold voltage is found to increase with FGA treatment, as shown in Figure 3 It is known that traps at the Al 2 O 3 /InGaAs interface are mostly donor type. The reduction of donor interface trap does not have a significant impact on the threshold voltage while the reduction of acceptor trap leads to negative V T shift [15]. Thus, the positive shift of V T in this study is attributed to the reduction of positive fixed charge density and the ion charge density in oxide layer. Figure 4 (a) shows the comparison of on-current. I on is found to increase by 14% on average with FGA, accompanied by 25% g m enhancement (not shown). One origin for the I on enhancement is the reduction of interface trap density near the conduction band edge. Another origin is that mobility is improved due to the reduction in Coulomb scattering as a result of oxide charge reduction.
Interface trap density of the devices are extracted with the approximate formula SS = 60(1 + (qD it + C D )/C ox ) mV/dec [16], where C D is the depletion capacitance and C ox is the gate capacitance. The depletion capacitance can be neglected for its weak impact on SS. Devices in [4] shows the minimum SS of 63mV/dec, which indicates C D contribute to at most 3mV/dec to SS in the InGaAs GAA MOSFET structure. As the device structure is similar as [4], C D is also negligible in this work. Thus, subthreshold swing can be written as SS = 60(1 + qD it /C ox ) mV/dec. It is estimated that the upper limit of mid-gap D it is reduced by 40% percent with FGA, indicating that FGA can improve the interface quality of the Al 2 O 3 /InGaAs interface.
Another interesting phenomenon found in this work is the standard deviation (STD) comparison for SS, V T , and I on . The SS STD and V T STD of devices with FGA are smaller than the control devices without FGA, while the I on STD and g m STD of devices with FGA are larger than devices without FGA. The STD of SS and V T reduces with FGA treatment because of the improvement of the interface quality as shown earlier.
However, the larger on-state STD seems unexpected and contradictory to the D it reduction. The most possible reason is that the ohmic contact of the devices with FGA is worse than those without FGA, which can in turn increase on-state variation. To confirm this hypothesis, external resistance (R ext ) is extracted by linear fitting R tot and 1/(V gs -V t -V ds /2) at small V ds [17]. As shown in Figure 4 (b), both average value of R ext and STD of R ext of devices with FGA is much larger than devices without FGA. The larger R ext of devices with FGA suggests that the intrinsic current improvement of devices with FGA is even larger than that shown in Figure 4 (a). Though the exact reason for the increased R ext after FGA has not been clearly understood, it is likely that the Au/Ge/Ni alloy based ohmic contact is sensitive to FGA treatment. More advanced source/drain contact technologies need to be explored to reduce the R ext and improve on-state variation.
Furthermore, we investigate the scaling metrics of InGaAs GAA MOSFETs with 6nm T NW and FGA. The T NW scaling of an InGaAs GAA MOSFET theoretically has the same effect as the W NW scaling in terms of the electrostatic control [4]. However, the scaling of T NW can reduce the surface area that has underwent dry etching process during the nanowire formation, leading to the reduced surface roughness. Figure 5 shows SS and DIBL versus L ch with W NW =30nm. No evidence of L ch dependence of SS and DIBL are observed in this work, as opposed to the InGaAs GAA MOSFETs with larger T NW [4].
The results show that the InGaAs GAA MOSFETs with extremely thin T NW offer better immunity to SCE and improved scalability which can be further improved by equivalent oxide thickness (EOT) scaling [4,18,19].
In conclusion, InGaAs GAA MOSFETs with 6nm T NW have been fabricated. The effects of FGA on the performance of the devices are systematically studied. It is found that the 30min 400 Forming Gas Anneal results in a improved Al 2 O 3 /InGaAs interface and is also fully compatible with the (NH 4 ) 2 S passivation. A scaling metrics study of the InGaAs GAA MOSFETs has also been carried out. The extremely thin nanowire structure has been shown to improve SCE immunity and it is very promising for future logic applications.