Now showing items 1-20 of 21

    • The accelerator store 

      Lyons, Michael; Hempstead, Mark; Wei, Gu-Yeon; Brooks, David M. (Association for Computing Machinery (ACM), 2012)
      In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor ...
    • An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS 

      Hempstead, Mark; Brooks, David M.; Wei, Gu-Yeon (Institute of Electrical & Electronics Engineers (IEEE), 2011)
      Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Reducing power consumption requires the development ...
    • Applied inference 

      Lee, Benjamin C.; Brooks, David M. (Association for Computing Machinery (ACM), 2010)
      We propose and apply a new simulation paradigm for microarchitectural design evaluation and optimization. This paradigm enables more comprehensive design studies by combining spatial sampling and statistical inference. ...
    • Design and Test Strategies for Microarchitectural PostFabrication 

      Liang, Xiaoyao; Lee, Benjamin; Wei, Gu-Yeon; Brooks, David M. (2008)
      Process variations are the major hurdle for continued technology scaling. Both systematic and random variations will affect the critical delay of fabricated chips, causing a wide frequency and power distribution. Tuning ...
    • Dimetrodon: Processor-level Preventive Thermal Management via Idle Cycle Injection 

      Bailis, Peter; Reddi, Vijay Janapa; Gandhi, Sanjay; Brooks, David M.; Seltzer, Margo I. (ACM, 2011)
      Processor-level dynamic thermal management techniques have long targeted worst-case thermal margins. We examine the thermal-performance trade-offs in average-case, preventive thermal management by actively degrading ...
    • Eliminating voltage emergencies via software-guided code transformations 

      Reddi, Vijay Janapa; Campanoni, Simone; Gupta, Meeta S.; Smith, Michael D.; Wei, Gu-Yeon; Brooks, David M.; Hazelwood, Kim (Association for Computing Machinery (ACM), 2010)
      In recent years, circuit reliability in modern high-performance processors has become increasingly important. Shrinking feature sizes and diminishing supply voltages have made circuits more sensitive to microprocessor ...
    • Empirical Performance Models for 3TID Memories 

      Lovin, Kristen; Lee, Benjamin; Liang, Xiaoyao; Brooks, David M.; Wei, Gu-Yeon (2008)
      Abstract—Process variation poses a significant threat to the performance and reliability of the 6T SRAM cell. In response, research has turned to new memory cell models, such as the 3T1D DRAM cell, as potential replacement ...
    • Evaluation of voltage stacking for near-threshold multicore computing 

      Lee, Sae Kyu; Brooks, David M.; Wei, Gu-Yeon (ACM, 2012)
      This paper evaluates voltage stacking in the context of near-threshold multicore computing. Key attributes of voltage stacking are investigated using results from a test-chip prototype built in 150nm FDSOI CMOS. By "stacking" ...
    • A fully integrated battery-connected switched-capacitor 4:1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling 

      Tong, Tao; Zhang, Xuan; Kim, Wonyoung; Brooks, David M.; Wei, Gu-Yeon (2016-02-24)
      This work presents a switched-capacitor (SC) DC-DC voltage regulator that converts a 3.7V battery voltage down to ~0.8V in order to power the `brain' SoC of a flapping-wing microrobotic bee. A cascade of two 2:1 SC converters ...
    • A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation 

      Kim, Wonyoung; Brooks, David M.; Wei, Gu-Yeon (IEEE, 2011)
      In recent years, chip multiprocessor architectures have emerged to scale performance while staying within tight power constraints. This trend motivates per core/block dynamic voltage and frequency scaling (DVFS) with fast ...
    • The HELIX project 

      Campanoni, Simone; Jones, Timothy Mark; Holloway, Glenn H.; Wei, Gu-Yeon; Brooks, David M. (IEEE, 2012)
      Parallelism has become the primary way to maximize processor performance and power efficiency. But because creating parallel programs by hand is difficult and prone to error, there is an urgent need for automatic ways of ...
    • HELIX: Automatic Parallelization of Irregular Programs for Chip Multiprocessing. 

      Campanoni, Simone; Jones, Timothy; Holloway, Glenn H.; Reddi, Vijay Janapa; Wei, Gu-Yeon; Brooks, David M. (Association for Computing Machinery, 2012)
      We describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns successive iterations of a loop to separate threads. We show that the inter-thread communication costs forced by loop-carried ...
    • Helix: Making the Extraction of Thread-Level Parallelism Mainstream 

      Campanoni, Simone; Jones, Timothy Mark; Holloway, Glenn H.; Wei, Gu-Yeon; Brooks, David M. (Institute of Electrical & Electronics Engineers (IEEE), 2012)
      Improving system performance increasingly depends on exploiting microprocessor parallelism, yet mainstream compilers still don't parallelize code automatically. Helix automatically parallelizes general-purpose programs ...
    • Measuring Code Optimization Impact on Voltage Noise 

      Kanev, Svilen; Jones, Timothy M.; Wei, Gu-Yeon; Brooks, David M.; Janapa Reddi, Vijay (2013)
      In this paper, we characterize the impact of compiler optimizations on voltage noise. While intuition may suggest that the better processor utilization ensured by optimizing compilers results in a small amount of voltage ...
    • Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators 

      Kim, Wonyoung (2013-03-18)
      Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and ...
    • Regression Modeling Strategies for Microarchitectural Performance and Power Prediction 

      Lee, Benjamin C.; Brooks, David M. (2006)
      We propose regression modeling as an effective approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a large microarchitectural design space. ...
    • Shrink-Fit: A Framework for Flexible Accelerator Sizing 

      Lyons, Michael; Wei, Gu-Yeon; Brooks, David M. (Institute of Electrical & Electronics Engineers (IEEE), 2013)
      RTL design complexity discouraged adoption of reconfigurable logic in general purpose systems, impeding opportunities for performance and energy improvements. Recent improvements to HLS compilers simplify RTL design and ...
    • Toward a Hardware Accelerated Future 

      Lyons, Michael John (2013-10-18)
      Hardware accelerators provide a rare opportunity to achieve orders-of-magnitude performance and power improvements with customized circuit designs.
    • Voltage Noise in Production Processors 

      Janapa Reddi, Vijay; Kanev, Svilen; Kim, Wonyoung; Campanoni, Simone; Smith, Michael D.; Wei, Gu-Yeon; Brooks, David M. (Institute of Electrical & Electronics Engineers (IEEE), 2011)
      Voltage variations are a major challenge in processor design. Here, researchers characterize the voltage noise characteristics of programs as they run to completion on a production Core 2 Duo processor. Furthermore, they ...
    • Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling 

      Reddi, Vijay Janapa; Kanev, Svilen; Kim, Wonyoung; Campanoni, Simone; Smith, Michael D.; Wei, Gu-Yeon; Brooks, David M. (IEEE, 2010)
      Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel Core2 ...