GaAs Enhancement-Mode NMOSFETs Enabled by Atomic Layer Epitaxial \(La_{1.8}Y_{0.2}O_3\) as Dielectric

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GaAs Enhancement-Mode NMOSFETs Enabled by Atomic Layer Epitaxial \(La_{1.8}Y_{0.2}O_3\) as Dielectric

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Title: GaAs Enhancement-Mode NMOSFETs Enabled by Atomic Layer Epitaxial \(La_{1.8}Y_{0.2}O_3\) as Dielectric
Author: Gordon, Roy Gerald; Dong, L.; Wang, X. W.; Zhang, J. Y.; Ye, P. D.; Li, X. F.

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Citation: Dong, L., X. W. Wang, J. Y. Zhang, X. F. Li, Roy Gerald Gordon, and P. D. Ye. Forthcoming. GaAs enhancement-mode NMOSFETs enabled by atomic layer epitaxial \(La_{1.8}Y_{0.2}O_3\) as dielectric. IEEE Electron Device Letters.
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Abstract: We demonstrate high performance enhancement-mode (E-mode) GaAs NMOSFETs with an epitaxial gate dielectric layer of \(La_{1.8}Y_{0.2}O_3\) grown by atomic layer epitaxy (ALE) on GaAs(111)A substrates. A \(0.5-\mu m\)-gate-length device has a record-high maximum drain current of 336 mA/mm for surface-channel E-mode GaAs NMOSFETs, a peak intrinsic transconductance of 210 mS/mm, a subthreshold swing of 97 mV/dec and an \(I_{ON}/I_{OFF}\) ratio larger than \(10^7\). Thermal stability of the single crystalline \(La_{1.8}Y_{0.2}O_3\)-single crystalline GaAs interface is investigated by capacitance-voltage (C-V) and conductance-voltage (G-V) analysis. High temperature annealing is found to be effective to reduce the \(D_{it}\).
Terms of Use: This article is made available under the terms and conditions applicable to Open Access Policy Articles, as set forth at http://nrs.harvard.edu/urn-3:HUL.InstRepos:dash.current.terms-of-use#OAP
Citable link to this page: http://nrs.harvard.edu/urn-3:HUL.InstRepos:10265396
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