Variability Improvement by Interface Passivation and EOT Scaling of InGaAs Nanowire MOSFETs

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Variability Improvement by Interface Passivation and EOT Scaling of InGaAs Nanowire MOSFETs

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Title: Variability Improvement by Interface Passivation and EOT Scaling of InGaAs Nanowire MOSFETs
Author: Gu, Jiangjiang J.; Wang, Xinwei; Wu, Heng; Gordon, Roy Gerald; Ye, Peide D.

Note: Order does not necessarily reflect citation order of authors.

Citation: Gu, Jiangjiang J., Xinwei Wang, Heng Wu, Roy G. Gordon, and Peide D. Ye. 2013. Variability improvement by interface passivation and EOT scaling of InGaAs nanowire MOSFETs. IEEE Electron Device Letters 34(5): 608-610.
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Abstract: High-performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (\(L_{ch}\)) down to 20 nm are fabricated by integrating a higher-k \(LaAlO_3\)-based gate-stack with an equivalent oxide thickness of 1.2nm. It is found that inserting an ultrathin (0.5 nm) \(Al_2O_3\) interfacial layer between the higher k \(LaAlO_3\) and InGaAs can significantly improve the interface quality and reduce device variation. As a result, a record low subthreshold swing of 63 mV/dec is demonstrated at sub-80-nm \(L_{ch}\) for the first time, making InGaAs GAA nanowire devices a strong candidate for future low-power transistors.
Published Version: doi:10.1109/LED.2013.2248114
Terms of Use: This article is made available under the terms and conditions applicable to Open Access Policy Articles, as set forth at http://nrs.harvard.edu/urn-3:HUL.InstRepos:dash.current.terms-of-use#OAP
Citable link to this page: http://nrs.harvard.edu/urn-3:HUL.InstRepos:11169839
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