Show simple item record

dc.contributor.authorYao, Jun
dc.contributor.authorYan, Hao
dc.contributor.authorDas, Shamik
dc.contributor.authorKlemic, James F.
dc.contributor.authorEllenbogen, James C.
dc.contributor.authorLieber, Charles M.
dc.date.accessioned2014-03-05T21:36:07Z
dc.date.issued2014
dc.identifierQuick submit: 2014-01-31T11:52:45-05:00
dc.identifier.citationYao, J., H. Yan, S. Das, J. F. Klemic, J. C. Ellenbogen, and C. M. Lieber. 2014. “Nanowire nanocomputer as a finite-state machine.” Proceedings of the National Academy of Sciences (January 27). doi:10.1073/pnas.1323818111. http://dx.doi.org/10.1073/pnas.1323818111.en_US
dc.identifier.issn1091-6490en_US
dc.identifier.urihttp://nrs.harvard.edu/urn-3:HUL.InstRepos:11859323
dc.description.abstractImplementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly-organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine (nanoFSM). The system was fabricated using a design- oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoFSM through modular design employing a multi-tile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoFSM integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive inter-tile and intra-tile communication that exhibits rigorous input/output (I/O) matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a FSM or computer. The programmable multi-tile circuit was also re-programmed to a functionally-distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our new design-oriented deterministic methodology to yield more extensive multi-tile systems, suggest that proposed general-purpose nanocomputers can be realized in the near future.en_US
dc.description.sponsorshipChemistry and Chemical Biologyen_US
dc.description.sponsorshipEngineering and Applied Sciencesen_US
dc.language.isoen_USen_US
dc.publisherProceedings of the National Academy of Sciencesen_US
dc.relation.isversionofdoi:10.1073/pnas.1323818111en_US
dash.licenseLAA
dc.titleNanowire nanocomputer as a finite-state machineen_US
dc.typeJournal Articleen_US
dc.date.updated2014-01-31T16:54:17Z
dc.description.versionAccepted Manuscripten_US
dc.rights.holderJ Yao, H Yan, S Das, JF Klemic, JC Ellenbogen and CM Lieber
dc.relation.journalProceedings of the National Academy of Sciencesen_US
dash.depositing.authorLieber, Charles M.
dash.waiver2014-01-01
dc.date.available2014-03-05T21:36:07Z
dc.identifier.doi10.1073/pnas.1323818111*
workflow.legacycommentsPer Sherpa Romeo can post LAA http://www.sherpa.ac.uk/romeo/issn/1091-6490/en_US
dash.contributor.affiliatedYao, Jun
dash.contributor.affiliatedLieber, Charles


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record