Design and Test Strategies for Microarchitectural PostFabrication

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Design and Test Strategies for Microarchitectural PostFabrication

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Title: Design and Test Strategies for Microarchitectural PostFabrication
Author: Liang, Xiaoyao; Lee, Benjamin; Wei, Gu-Yeon; Brooks, David M.

Note: Order does not necessarily reflect citation order of authors.

Citation: Liang, Xiaoyao, Benjamin Lee, Gu-Yeon Wei, and David Brooks. 2008. Design and Test Strategies for Microarchitectural PostFabrication. Harvard Computer Science Group Technical Report TR-06-08.
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Abstract: Process variations are the major hurdle for continued technology scaling. Both systematic and random variations will affect the critical delay of fabricated chips, causing a wide frequency and power distribution. Tuning techniques are capable of adapting the microarchitecture to mitigate the impact of variations at post-fabrication testing time. Most of the existing techniques ignore testing cost or simply assume a naive exhaustive testing scheme. But testing has associated costs, which might be prohibitively expensive for a large space of post-fabrication tuning configurations. This paper proposes a new post-fabrication testing framework that accounts for testing costs. This framework uses on-chip canary circuits to capture systematic variation while using statistical analysis to estimate random variation. Regression model is applied to predict the chip performance and power. These techniques comprise an integrated framework that identifies the most energy efficient post-fabrication tuning configuration for each chip. The testing cost for the proposed framework is low, usually converging with fewer than two rounds of tests. At low cost, the proposed test framework can achieve 93 to 96 percent of BIP S3 optimal tuning results, even under very large variations. Furthermore, the test framework fits into existing test flows without major changes to testing facilities.
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