Performance Modeling of Distributed Memory Architectures

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Performance Modeling of Distributed Memory Architectures

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Title: Performance Modeling of Distributed Memory Architectures
Author: Johnsson, S. Lennart
Citation: Johnsson, S. Lennart. 1991. Performance Modeling of Distributed Memory Architectures. Harvard Computer Science Group Technical Report TR-10-91.
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Abstract: We provide performance models for several primitive operations on data structures distributed over memory units interconnected by a Boolean cube network. In particular, we model single source, and multiple source concurrent broadcasting or reduction, concurrent gather and scatter operations, shifts along several axes of multi-dimensional arrays, and emulation of butterfly networks. We also show how the processor configuration, data aggregation, and the encoding of the address space affect the performance for two important basic computations: the multiplication of arbitrarily shaped matrices, and the Fast Fourier Transform. We also give an example of the performance behavior for local matrix operations for a processor with a single path to local memory, and a set of registers. The analytic models are verified by measurements on the Connection Machine model CM-2.
Terms of Use: This article is made available under the terms and conditions applicable to Other Posted Material, as set forth at http://nrs.harvard.edu/urn-3:HUL.InstRepos:dash.current.terms-of-use#LAA
Citable link to this page: http://nrs.harvard.edu/urn-3:HUL.InstRepos:24947960
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