Measuring Code Optimization Impact on Voltage Noise

 
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Jones, Timothy M.
Janapa Reddi, Vijay
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https://doi.org/10.pdf
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Kanev, Svilen, Timothy M. Jones, Gu-Yeon Wei, David Brooks, and Vijay Reddi. 2013. “Measuring Code Optimization Impact on Voltage Noise.” In the Proceedings of the 9th Silicon Errors in Logic - System Effects Workshop (SELSE 9), Palo Alto, California, March 26 – 27, 2013.
Abstract
In this paper, we characterize the impact of compiler optimizations on voltage noise. While intuition may suggest that the better processor utilization ensured by optimizing compilers results in a small amount of voltage variation, our measurements on a Intel® Core™2 Due Processor show the opposite - the majority of SPEC 2006 benchmarks exhibit more voltage droops when aggressively optimized. We show that this increase in noise could be sufficient for a net performance decrease in a typical case, resilient design.
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http://www.eecs.harvard.edu/~skanev/papers/selse13vopt.pdf
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This article is made available under the terms and conditions applicable to Open Access Policy Articles, as set forth at http://nrs.harvard.edu/urn-3:HUL.InstRepos:dash.current.terms-of-use#OAP
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http://nrs.harvard.edu/urn-3:HUL.InstRepos:25415919

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