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dc.contributor.authorHempstead, Mark
dc.contributor.authorBrooks, David M.
dc.contributor.authorWei, Gu-Yeon
dc.date.accessioned2016-08-02T16:09:53Z
dc.date.issued2011
dc.identifier.citationHempstead, Mark, David Brooks, and Gu-Yeon Wei. 2011. “An Accelerator-Based Wireless Sensor Network Processor in 130 Nm CMOS.” IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (2) (June): 193–202. doi:10.1109/jetcas.2011.2160751.en_US
dc.identifier.issn2156-3357en_US
dc.identifier.urihttp://nrs.harvard.edu/urn-3:HUL.InstRepos:27770104
dc.description.abstractNetworks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Reducing power consumption requires the development of system-on-chip implementations that must provide both energy efficiency and adequate performance to meet the demands of the long deployment lifetimes and bursts of computation that characterize wireless sensor network (WSN) applications. Therefore, this work argues that designers should evaluate the design in terms of average power for an entire workload, including active and idle periods, not just the metric of energy-per-instruction.en_US
dc.description.sponsorshipEngineering and Applied Sciencesen_US
dc.language.isoen_USen_US
dc.publisherInstitute of Electrical & Electronics Engineers (IEEE)en_US
dc.relation.isversionofdoi:10.1109/JETCAS.2011.2160751en_US
dc.relation.hasversionhttps://www.eecs.harvard.edu/~dbrooks/hempstead_cases09.pdfen_US
dash.licenseOAP
dc.titleAn Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOSen_US
dc.typeJournal Articleen_US
dc.description.versionAccepted Manuscripten_US
dc.relation.journalIEEE Journal on Emerging and Selected Topics in Circuits and Systemsen_US
dash.depositing.authorBrooks, David M.
dc.date.available2016-08-02T16:09:53Z
dc.identifier.doi10.1109/JETCAS.2011.2160751*
dash.contributor.affiliatedBrooks, David
dash.contributor.affiliatedWei, Gu-Yeon


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