Tsai, Yi-MinHuang, Kang-YenKung, H.Vlah, DarioGwon, YoungjuneChen, Liang-Gee2012-12-052012Tsai, Yi-Min, Keng-Yen Huang, H. T. Kung, Dario Vlah, Youngjune Gwon, and Liang-Gee Chen. 2012. A chip architecture for compressive sensing based detection of IC trojans. 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, South Korea, May 20-23, 2012.97814673021731467302171http://nrs.harvard.edu/urn-3:HUL.InstRepos:10000895We present a chip architecture for a compressive sensing based method that can be used in conjunction with the JTAG standard to detect IC Trojans. The proposed architecture compresses chip output resulting from a large number of test vectors applied to a circuit under test (CUT). We describe our designs in sensing leakage power, computing random linear combinations under compressive sensing, and piggybacking these new functionalities on JTAG. Our architecture achieves approximately a 10× speedup and 1000× reduction in output bandwidth while incurring a small area overhead.en-UScompressive sensingCS-JTAGmeasurement generatorIC TrojanMonograph or Book2012-12-0510.1109/SiPS.2012.33