Gu, J.J.Wang, XinweiShao, J.Neal, A.T.Manfra, M.J.Gordon, RoyYe, P.D.2012-12-072012Gu, J. J., X. W. Wang, J. Shao, A.T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye. 2012. III-V 4D Transistors. In Proceedings of the 70th Annual Device Research Conference (DRC 2012), June 18-20, 2012, University Park, Pennsylvania. Piscataway: Ieee Press Books.978146731163214673116341548-3770http://nrs.harvard.edu/urn-3:HUL.InstRepos:10021409We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with \(3×4\) arrays show high drive current of \(1.35mA/ \mu m\) and high transconductance of \(0.85mS/ \mu m\). The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.en-USfabricationindium gallium arsenideindium phosphidelogic gatesMOSFETsnanobiosciencenanoscale devicesIII-V semiconductorsMOSFETindium compoundsIII-V 4D transistorIII-V gate-all-around nanowire MOSFETInGaAsRF applicationdrivability bottlenecklaterally integrated III-V 4D transistorlow-power logic applicationnanowire devicetransconductancevertical stackingvertically integrated III-V 4D transistorMonograph or Book2012-12-0710.1109/DRC.2012.6256964