Person:

Au, Yeung

The packing density of microelectronic devices has increased exponentially over the past four decades. Continuous enhancements in device performance and functionality have been achieved by the introduction of new materials and fabrication techniques. This thesis summarizes the thin film materials and metallization processes by chemical vapor deposition (CVD) developed during my graduate study with Professor Gordon at Harvard University. These materials and processes have the potential to build future generations of microelectronic devices with higher speeds and longer lifetimes. Manganese Silicate Diffusion Barrier: Highly conformal, amorphous and insulating manganese silicate ((MnSi_xO_y)) layers are formed along the walls of trenches in interconnects by CVD using a manganese amidinate precursor vapor that reacts with the surfaces of the insulators. These ((MnSi_xO_y)) layers are excellent barriers to diffusion of copper, oxygen and water. Manganese Capping Layer: A selective CVD manganese capping process strengthens the interface between copper and dielectric insulators to improve the electromigration reliability of the interconnects. High selectivity is achieved by deactivating the insulator surfaces using vapors containing reactive methylsilyl groups. Manganese at the Cu/insulator interface greatly increases the strength of adhesion between the copper and the insulator. Bottom-up Filling of Copper and Alloy in Narrow Features: Narrow trenches, with widths narrow than 30 nm and aspect ratios up to 9:1, can be filled with copper or copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. A conformal manganese nitride ((Mn_4N)) layer serves as a diffusion barrier and adhesion layer. Iodine atoms chemisorb on the (Mn_4N) layer and are then released to act as a catalytic surfactant on the surface of the growing copper layer to achieve void-free, bottom-up filling. Upon post-annealing, manganese in the alloy diffuses out from the copper and forms a self-aligned barrier in the surface of the insulator. Conformal Seed Layers for Plating Through-Silicon Vias: Through-silicon vias (TSV) will speed up interconnections between chips. Conformal, smooth and continuous seed layers in TSV holes with aspect ratios greater than 25:1 can be prepared using vapor deposition techniques. (Mn_4N) is deposited conformally on the silica surface by CVD to provide strong adhesion at Cu/insulator interface. Conformal copper or Cu-Mn alloy seed layers are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process.

Through-silicon vias (TSV) will speed up interconnections between chips. Manufacturable and cost-effective TSVs will allow faster computer systems. In this paper, we report the successful formation of seed layers for plating copper TSVs with aspect ratios greater than 25:1. Following the rapid atomic layer deposition (ALD) of a conformal insulating layer of silica inside the silicon vias, manganese nitride (Mn4N) is deposited conformally on the silica surface by chemical vapor deposition (CVD). Mn4N forms an effective copper diffusion barrier and provides strong adhesion between the silica and the subsequently-deposited copper. Conformal copper or copper-manganese alloy films are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process. Diffusion of manganese during post-deposition annealing further enhances the barrier and adhesion properties at the copper/dielectric interface

Barriers to prevent diffusion of copper, oxygen and water vapor were formed by CVD using a manganese precursor vapor that reacts with silica surfaces. The manganese metal penetrates only a few nanometers into the silica to make conformal amorphous manganese silicate layers. This MnSixOy was found to be an excellent barrier to the diffusion of Cu, O2 and H2O vapor. The adhesion strength of Cu to the MnSixOy was found to be sufficiently strong to satisfy the semiconductor industry requirements for interconnections in future microelectronic devices. CVD Mn dissolves into copper surfaces and then diffuses to increase adhesion to SiCNO capping layers.

We present a process for the void-free filling of sub-100 nm trenches with copper or copper-manganese alloy by chemical vapor deposition (CVD). Conformally deposited manganese nitride serves as an underlayer that initially chemisorbs iodine. CVD of copper or copper-manganese alloy releases the adsorbed iodine atoms from the surface of the manganese nitride, allowing iodine to act as a surfactant catalyst floating on the surface of the growing copper layer. The iodine increases the growth rate of the copper and manganese by an order of magnitude. As the iodine concentrates near the narrowing bottoms of features, void-free, bottom-up filling of CVD of pure copper or copper-manganese alloy is achieved in trenches narrower than 30 nm with aspect ratios up to at least 5:1. The manganese nitride films also show barrier properties against copper diffusion and enhance adhesion between copper and dielectric insulators. During post-deposition annealing, manganese in the alloy diffuses out from copper through the grain boundaries and forms a self-aligned layer that further improves adhesion and barrier properties at the copper/insulator interface. This process provides nanoscale interconnects for microelectronic devices with higher speeds and longer lifetimes.