Person:

Tong, Tao

This work presents a switched-capacitor (SC) DC-DC voltage regulator that converts a 3.7V battery voltage down to ~0.8V in order to power the `brain' SoC of a flapping-wing microrobotic bee. A cascade of two 2:1 SC converters offers high efficiency for a 4:1 conversion ratio. A charge recycling technique reduces the flying capacitor's bottom-plate parasitic loss by 50% and overall conversion efficiency reaches 70%. The output droop is less than 10% of the nominal output voltage for a worst-case 47mA load step.

Traditional power delivery solutions f or system-on-chip (SoC) applications rely on off-chip voltage regulators. The off-chip power delivery solution is becoming a bottleneck for SoCs, due to 1) coarse voltage domain management, 2) increased cost as well as complexity of the power delivery network, and 3) high I2R loss as supply voltages scale down with the fabrication technology. One promising solution is to integrate the voltage regulators in the SoC. While fully integrated voltage regulators (FIVRs) could resolve these problems, their performance is limited by low efficiency and high chip area overhead, especially if the conversion ratio of the converter is high (≥ 4 to-1). This thesis presents the design and implementation of two fully integrated switched-capacitor (SC) DC-DC voltage regulators. Both regulators are implemented in the SoC along with the microprocessors they deliver power to. I first present a two-stage 4-to-1 SC regulator in a flapping wing micro-robotic bee application. The regulator converts a 3.7V battery voltage down to two lower voltages (~1.8V and ~0.9V) for the rest of the circuits in the SoC. The two-stage topology and the proposed charge recycling technique improve conversion efficiency and provide very fast load regulation to handle the dynamic current fluctuation of the load circuitry. Next, I explore the power delivery architecture at the system level and propose a joint power delivery network that combines SC FIVRs with voltage stacking. Voltage stacking reduces the maximal power that the FIVRs have to provide and “hides” the FIVR conversion loss so that the latter only applies to a portion of the total power consumed by the load. The FIVRs reduce the voltage noise of the stacked voltage domains when the load in the stacked voltage domains consumes a different amount of power. To verify the benefits of this new power delivery system, a fully integrated reconfigurable SC regulator is implemented with 16 Intel microcontroller cores that are stacked in four voltage domains. The SC regulator simultaneously provides power to the four stacked voltage domains (~0.9V) from a single input voltage (~3.6V). The regulator can dynamically change its configuration to optimize its performance according to the current profiles of the stacked load. A hybrid feedback control scheme is implemented to simultaneously regulate the four stacked domains. The proposed power delivery system achieves an average efficiency of 87% and a peak efficiency of 99%. At the end of this thesis, I present my conclusion and discuss the technologies that could further improve FIVR-based power delivery systems in the future.