Optimizing Electronic-Photonic Transceiver Circuits for Energy-Efficient Data Communication

Abstract

Data communication continues to be a major bottleneck for energy-efficient computing, especially for today's warehouse-scale datacenters that now comprise hundreds of thousands of interconnected graphics processing units (GPUs). For these datacenters, long interconnects (~100 meters) are now transitioning from electrical links to optical links, which use electronic–photonic transceiver circuits to communicate data using light. Currently, silicon photonics (SiPh) is widely used to implement these electronic–photonic integrated circuits (EPICs), due to its compatibility with existing infrastructure for silicon electronics, rather than necessarily offering the most energy-efficient material platform for EPICs. Looking forward, heterogeneous integration of beyond-silicon technologies is a promising direction to improve energy efficiency and data rates, and is the focus of this dissertation. Despite its promise, three key challenges are: (1) identifying the optimal combination of emerging technologies to use within a massive design space for EPICs, (2) experimentally overcoming non-idealities and fabrication variations, and (3) scaling up towards photonics VLSI. To address these challenges, I first create a roadmap for developing EPIC transceivers, by quantitatively evaluating technology combinations across the full EPIC design space. From this analysis, I identify 8-level pulse amplitude modulation (PAM-8) as a promising direction to improve energy efficiency (energy per bit) and data rate (TB/s) through two key technologies that improve noise resilience: (i) on the transmitter side (TX), using a micro-ring modulator (MRM) engineered segment length (ESL) digital-to-optical converter (DOC), which I describe in detail in this dissertation. A DOC converts digital electrical signals directly to analog optical signals, eliminating the need for electrical digital-to-analog converters (DACs) and improving energy efficiency. ESL is a design technique that uses segmented electro-optic (EO) modulators, where the length of each segment is specifically engineered to achieve evenly spaced transmitted optical power levels. The MRM is the design choice for the underlying EO modulator due to its smaller area footprint vs. other EO modulators, such as Mach–Zehnder modulators (MZMs); (ii) on the receiver side (RX), using a trans-impedance amplifier (TIA) implemented in silicon–germanium heterojunction bipolar transistor (SiGe HBT) technology, which offers better trade-offs in supply voltage (enabling increased symbol spacing after optical-to-electrical conversion) and bandwidth, compared to silicon CMOS technologies for digital logic. I show that combining these advances for TX & RX enables 200 Gbps per channel at a bit error rate (BER) of 1×10⁻⁸ with 2.89 pJ/bit - representing a more than 2× improvement vs. a state-of-the-art 112 Gbps SiPh transceiver with 7.14 pJ/bit for the same overall data rate - while also improving overall area footprint. These results, which are consistent with values reported for EPIC transceivers in production, are derived from detailed electronic–photonic circuit simulations using: (a) compact models for photonic devices I developed and calibrated to physics simulations and experimental data, and (b) industry-standard Process Design Kits (PDKs) for state-of-the-art electronics technologies. Furthermore, my roadmap for EPIC transceivers also includes concrete paths for continued improvements in energy efficiency and data rates. In particular, I identify multiple paths to achieve 1 pJ/bit through coordinated improvements in electronics and photonics. One such path includes advances in field-effect transistors (FinFETs to gate-all-around FETs) and improvements in modulation efficiency of barium titanate (BTO), quantified by Vπ·L (the product of modulator length L and the voltage required to shift the relative phase of an incoming optical signal by π radians, Vπ). These paths directly guide experimental research on EPIC transceiver circuits. Toward realizing these benefits in practice, my collaborators and I experimentally demonstrated the MRM-ESL-DOC that I identified above as being the most energy-area-efficient EO modulator. For my second contribution, I present the design techniques that enabled this MRM-ESL-DOC to achieve near-perfect spacing of optical power levels for PAM-8. By combining 3 design techniques: (i) engineered segment lengths (ESL, for segmented EO modulators), (ii) thermometer encoding of digital drive signals, and (iii) supply-voltage calibration for each segment, our fabricated DOCs exhibit near-zero non-linearity (quantified by INL: Integral Non-Linearity & DNL: Differential Non-Linearity), in a manner that is robust to both: (a) imperfections in fabrication, and (b) fringing electric fields in physical layouts of DOCs. As experimental validation, we fabricate an MRM-ESL-DOC in thin-film lithium niobate (TFLN), to realize PAM-8 with the best measured root-mean-squared values of INL = 0.04 least significant bits (LSBs) & DNL = 0.07 LSBs. These measurements represent 3.1× & 1.4× benefit in INL & DNL vs. a linearized MRM-DOC in silicon, and 1.9× & 1.2× benefit in INL & DNL vs. our previous MZM-ESL-DOC in TFLN. Finally, as photonic ICs continue to scale in photonic device count and in complexity, manual design and verification become increasingly time-consuming, motivating the need for automation, as is the case with VLSI design for electronic ICs. To enable VLSI design for photonic ICs, I show how to repurpose the mature electronic design automation (EDA) tools - developed in industry with significant investment over decades and optimized for large-scale electronic IC design - to perform photonic design automation. To do so, I introduce Photonic-to-Electronic and Electronic-to-Photonic transformations that enable photonic ICs to be designed using standard EDA tools. I show how to transform optical delay to electrical delay, as well as optical waveguide routing to electrical wire routing, enabling standard EDA tools to perform constraint-based timing and layout optimization on photonic ICs. I demonstrate scalability by automatically designing a tapeout-ready optical router with 832 devices in under an hour. These tools, validated for multi-billion-device electrical ICs, provide a path to scalable photonic IC design, even for multiple orders-of-magnitude higher number of photonic devices compared to photonic ICs today. Together, these contributions enable the quantitative design, experimental validation, and scalable implementation of energy-efficient EPICs for next-generation optical interconnects.