DreamRAM: A Fine-Grained Configurable Design Space Modeling and Exploration Tool for Custom 3D Die-Stacked Dynamic Random-Access Memory

Abstract

3D die-stacked Dynamic Random Access Memories (DRAMs), such as high-bandwidth memory (HBM), have emerged as a key technology for delivering high bandwidth and high memory density for applications such as high-performance computing, graphics, and machine learning (ML). However, different applications place diverse and sometimes diverging demands on the power, performance, and area of memory that cannot be universally satisfied with fixed commodity DRAM designs. 3D die-stacking creates the opportunity for an enormous DRAM design space through 3D integration and expanded total die area. To open and navigate this expansive design space of customized memory architectures that cater to application-specific needs, we introduce DreamRAM, a configurable bandwidth, capacity, energy, latency, and area modeling tool for custom 3D die-stacked DRAM designs. DreamRAM's large design space of 3D die-stacked DRAMs and DreamRAM's design space exploration tools enable designers to discover new DRAM design opportunities and weigh tradeoffs between DRAM designs catering to different application and system requirements. DreamRAM exposes fine-grained design customization parameters at the MAT, subarray, bank, and inter-bank levels, including extensions of partial page and subarray parallelism proposals found in the literature, to open a large and previously unexplored design space of DRAM configurations. DreamRAM analytically models wire pitch, width, length, capacitance, and scaling parameters to capture the performance tradeoffs of physical layout and routing design choices. Routing awareness enables DreamRAM to model a variety of MAT-level routing schemes regarding the placement of data and select lines over the MAT. DreamRAM is calibrated and validated against published industry HBM3 and HBM2E designs and against their JEDEC specifications. Within DreamRAM's rich design space, we identify designs that achieve each of 44% higher bandwidth, 125% higher capacity, 30% lower power, and 32% lower energy per bit compared to the baseline design, each on an iso-bandwidth, iso-capacity, and iso-power basis.