Nanoscale Magnetic Materials for Energy-Efficient Spin Based Transistors
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CitationIncorvia, Jean Anne Currivan. 2015. Nanoscale Magnetic Materials for Energy-Efficient Spin Based Transistors. Doctoral dissertation, Harvard University, Graduate School of Arts & Sciences.
AbstractIn this dissertation, I study the physical behavior of nanoscale magnetic materials and build spin-based transistors that encode information in magnetic domain walls. It can be argued that energy dissipation is the most serious problem in modern electronics, and one that has been resistant to a breakthrough. Wasted heat during computing both wastes energy and hinders further technology scaling. This is an opportunity for physicists and engineers to come up with creative solutions for more energy-efficient computing. I present the device we have designed, called domain wall logic (DW-Logic). Information is stored in the position of a magnetic domain wall in a ferromagnetic wire and read out using a magnetic tunnel junction. This hybrid design uses electrical current as the input and output, keeping the device compatible with charge- based transistors.
I build an iterative model to predict both the micromagnetic and circuit behavior of DW- Logic, showing a single device can operate as a universal gate. The model shows we can build complex circuits including an 18-gate Full Adder, and allows us to predict the device switching energy compared to complementary metal-oxide semiconductor (CMOS) transistors. Comparing ￼15 nm feature nodes, I find DW-Logic made with perpendicular magnetic anisotropy materials, and utilizing both spin torque transfer and the Spin Hall effect, could operate with 1000× reduced switching energy compared to CMOS.
I fabricate DW-Logic device prototypes and show in experiment they can act as AND and NAND gates. I demonstrate that one device can drive two subsequent devices, showing gain, which is a necessary requirement for fanout. I also build a clocked ring oscillator circuit to demonstrate successful bit propagation in a DW-Logic circuit and show that properly scaled devices can have improved operation.
Through building the devices, I develop a novel fabrication method for patterning sub-25 nm magnetic wires with very low (~ 2 nm) average edge roughness. I apply the fabrication method to measuring the Spin Hall angle in epitaxially grown thin films and to studying the repeatability of domain wall motion in narrow wires. I also present a number of modeling results, including the effect of edge roughness on both magnetic tunnel junctions and domain walls.
Citable link to this pagehttp://nrs.harvard.edu/urn-3:HUL.InstRepos:17467318
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