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Lee, Sae Kyu

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Sae Kyu

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Lee, Sae Kyu

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2012 - 20162

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Author's Publications: search.filters.isAuthorOfPublication.c32ec381-0991-4afa-8599-ffaf1cd82b4c

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    High Efficiency Power Delivery for Chip Multiprocessors Using Voltage Stacking
    (2016-09-08) Lee, Sae Kyu; Wei, Gu-Yeon; Brooks, David M.; Pfister, Hanspeter
    Efficient power delivery is a critical design target for modern computing systems. Inefficiencies in the power delivery network, coupled with increases in current draw and worsening current transients, significantly hinder energy-efficient power delivery for modern computing systems. Furthermore, off-chip components ostensibly have not scaled, exacerbating the power delivery challenges facing future computing systems. This thesis explores voltage stacking, an alternative power delivery solution that stacks voltage domains in series to deliver a high voltage to the chip rather than delivering a low voltage to the voltage domains in parallel. This results in reduction of overall current draw and alleviates off-chip power delivery inefficiencies. However, the trade-off of voltage stacking is increased complexity in mitigating inter-layer voltage noise and in efficient inter-layer communication. This thesis starts by exploring the characteristics of inter-layer voltage noise in voltage stacking. Results from a test chip prototype demonstrate the inherent properties of voltage stacking and show that supply rail impedance in voltage stacked systems depend on the overall current flow through the stack, leading to better noise immunity for high-throughput workload scenarios with higher overall power due to lower impedance across the voltage stack. Based on this understanding, the thesis presents a 16-core test chip that utilizes adaptive frequency clocking scheme with an efficient switched-capacitor DC-DC converter to mitigate voltage noise and improve system performance and efficiency. Experimental results demonstrate robust voltage noise mitigation and better than 94\% power delivery efficiency for high-throughput workload scenarios. Results also illustrate that augmenting the hardware techniques with intelligent workload allocation can preemptively reduce the inter-layer activity mismatch and further improve system power delivery efficiency. Next, to address the issue of efficient inter-layer communication, the thesis presents coupled inter-layer communication schemes. A test chip prototype demonstrates that by transmitting pulsed signals across capacitors and inductors to isolate the stacked voltage domains, the coupled layer shifters reliably shift signals across stack layer boundaries and enable efficient broadcasting of signals from one to multiple stack layers. Finally, the thesis concludes with future directions that can further improve performance and on-chip power delivery efficiency of voltage stacked systems.
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    Evaluation of voltage stacking for near-threshold multicore computing
    (ACM, 2012) Lee, Sae Kyu; Brooks, David; Wei, Gu-Yeon
    This paper evaluates voltage stacking in the context of near-threshold multicore computing. Key attributes of voltage stacking are investigated using results from a test-chip prototype built in 150nm FDSOI CMOS. By "stacking" logic blocks on top of each other, voltage stacking reduces the chip current draw and simplifies off-chip power delivery but within-die voltage noise due to inter-layer current mismatch is an issue. Results show that unlike conventional power delivery schemes, supply rail impedance in voltage stacked systems depend on aggregate power consumption, leading to better noise immunity for high power (low impedance) operation for many-core processors.