Publication: A Chip Architecture for Compressive Sensing Based Detection of IC Trojans
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Date
2012
Published Version
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Publisher
Institute of Electrical and Electronics Engineers
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Citation
Tsai, Yi-Min, Keng-Yen Huang, H. T. Kung, Dario Vlah, Youngjune Gwon, and Liang-Gee Chen. 2012. A chip architecture for compressive sensing based detection of IC trojans. 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, South Korea, May 20-23, 2012.
Research Data
Abstract
We present a chip architecture for a compressive sensing based method that can be used in conjunction with the JTAG standard to detect IC Trojans. The proposed architecture compresses chip output resulting from a large number of test vectors applied to a circuit under test (CUT). We describe our designs in sensing leakage power, computing random linear combinations under compressive sensing, and piggybacking these new functionalities on JTAG. Our architecture achieves approximately a 10× speedup and 1000× reduction in output bandwidth while incurring a small area overhead.
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Keywords
compressive sensing, CS-JTAG, measurement generator, IC Trojan
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