Publication: III-V 4D Transistors
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Date
2012
Published Version
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Publisher
Institute of Electrical and Electronics Engineers
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Citation
Gu, J. J., X. W. Wang, J. Shao, A.T. Neal, M. J. Manfra, R. G. Gordon, and P. D. Ye. 2012. III-V 4D Transistors. In Proceedings of the 70th Annual Device Research Conference (DRC 2012), June 18-20, 2012, University Park, Pennsylvania. Piscataway: Ieee Press Books.
Research Data
Abstract
We fabricated for the first time vertically and laterally integrated III-V 4D transistors. III-V gate-all-around (GAA) nanowire MOSFETs with \(3×4\) arrays show high drive current of \(1.35mA/ \mu m\) and high transconductance of \(0.85mS/ \mu m\). The vertical stacking of the III-V nanowires have provided an elegant solution to the drivability bottleneck of nanowire devices and is promising for future low-power logic and RF application.
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Keywords
fabrication, indium gallium arsenide, indium phosphide, logic gates, MOSFETs, nanobioscience, nanoscale devices, III-V semiconductors, MOSFET, indium compounds, III-V 4D transistor, III-V gate-all-around nanowire MOSFET, InGaAs, RF application, drivability bottleneck, laterally integrated III-V 4D transistor, low-power logic application, nanowire device, transconductance, vertical stacking, vertically integrated III-V 4D transistor
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