Variability Improvement by Interface Passivation and EOT Scaling of InGaAs Nanowire MOSFETs

Abstract

High-performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length ((L_{ch})) down to 20 nm are fabricated by integrating a higher-k (LaAlO_3)-based gate-stack with an equivalent oxide thickness of 1.2nm. It is found that inserting an ultrathin (0.5 nm) (Al_2O_3) interfacial layer between the higher k (LaAlO_3) and InGaAs can significantly improve the interface quality and reduce device variation. As a result, a record low subthreshold swing of 63 mV/dec is demonstrated at sub-80-nm (L_{ch}) for the first time, making InGaAs GAA nanowire devices a strong candidate for future low-power transistors.